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Course Detail

Degree
Master
Standard Academic Year
Course delivery methods
face-to-face
Subject
Mathematical sciences
Program
School
College of Electrical Engineering & Computer Science
Department
Campus
Classroom
Course Offering Year
Course Offering Month
September - November
Weekday and Period
Friday 234
Capacity
Credits
3
Language
English
Course Number
EEE5028

Logic Synthesis and Verification National Taiwan University

Course Overview

Logic synthesis is an automated process of generating logic circuits satisfying certain Boolean constraints and/or transforming logic circuits with respect to optimization objectives. It is an essential step in the design automation of VLSI systems and is crucial in extending the scalability of formal verification tools. This course introduces classic logic synthesis problems and solutions as well as some recent developments.

Learning Achievement

This course is intended to introduce Boolean algebra, Boolean function representation and manipulation, logic circuit optimization, circuit timing analysis, formal verification, and other topics. The students may learn useful Boolean reasoning techniques for various applications even beyond logic synthesis.

Competence

Course prerequisites

The prerequisite is the undergrad "Logic Design" course. Knowledge about data structures and programming would be helpful.

Grading Philosophy

Course schedule

Course type

Online Course Requirement

Instructor

JIE-HONG JIANG

Other information

Site for Inquiry

Please inquire about the courses at the address below.