Logic Synthesis and Verification National Taiwan University
Logic synthesis is an automated process of generating logic circuits satisfying certain Boolean constraints and/or transforming logic circuits with respect to optimization objectives. It is an essential step in the design automation of VLSI systems and is crucial in extending the scalability of formal verification tools. This course introduces classic logic synthesis problems and solutions as well as some recent developments.
This course is intended to introduce Boolean algebra, Boolean function representation and manipulation, logic circuit optimization, circuit timing analysis, formal verification, and other topics. The students may learn useful Boolean reasoning techniques for various applications even beyond logic synthesis.
The prerequisite is the undergrad "Logic Design" course. Knowledge about data structures and programming would be helpful.
Online Course Requirement
Site for Inquiry
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