Course Overview

1 Verification and test of critical and secure digital systems: Introduction (Context and issues; Verification vs Test; DO-254 Standard); Hardware systems verification (Simulation; Emulation & Prototyping); Hardware Testing (Defects and faults modeling; Automatic Test Pattern Generation (ATPG); Design for Test and Bult-in-Self-Test (DfT, BIST); Digital board testing (boundary scan).
2 HW/SW Co-Verification & Co-Development: Microelectronic context and trends (SoC, MPSOC); SoC design flow (Hadware/Software Co-design approach; Plateform based design); Introduction to SystemC (Starting with SystemC; Communication channels; New abstraction level: Transaction Level Modeling); Co-verification of Harware and Software systems (Context and definitions; Co-verification approaches based on ISS, BFM, TLM and emulation, criteria to choose a verification approach)
3 Hardware Security: Introduction & cryptography basis; Hardware Vulnerabilities (Fault Attacks; Side Chanel Attacks; Integrated Circuit Trustworthiness (Countermeasures, Security Certification and Case studies) Smartcard; FPGA)
Laboratories:
- VHDL & PSL Simulation with QuestaSim (Mentor GraphiCs)
- Simulation vs "prototyping and integrated logical analyzer" ChipScopePro (Xilinx)
- SRAM embedded memory test on FPGA Spartan 3 card (Xilinx)
- On the use of communication channels (Fifo, Mutex, Semaphore) to model a communication architecture
- SoCLib - "Emulation of a Hardware/Software architecture used for image processing"

http://esisar.grenoble-inp.fr/en/academics/verification-and-test-of-secure-circuits-5amse515

Learning Achievement

Competence

At the end of the lecture, the students will be able to verify, to test digital architectures and to analyse the vulnerabilities of embedded systemes. Then, they will be able to perform attacks and to design appropriate countermeasures.

Course prerequisites

Neccessary: Hardware Description Language (HDL, verilog or VHDL) for simulation (testbench) and design, logical synthesis, FPGA, processor architecture (processor models, instruction set architecture), C programming
Ideally: bases of object oriented programming

Grading Philosophy

Terminal Exam, First session, written, 3h, only document allowed "syntaxe VHDL", no calculator
Labs: average of laboratory exams

Course schedule

Course type

Lecture

Online Course Requirement

Instructor

David HELY; Vincent BEROULLE

Other information

Course content can evolve at any time before the start of the course. It is strongly recommended to discuss with the course contact about the detailed program.

Please consider the following deadlines for inbound mobility to Grenoble:
- April 1st, 2020 for Full Year (September to June) and Fall Semester (September to January) intake ;
- September 1st, 2020 for Spring Semester intake (February – June).

Site for Inquiry